1. Field of the Invention
The invention relates to integrated circuits and more particularly to the incorporation of auxiliary components, such as high-performance passive components or microelectromechanical systems, on an electronic chip.
2. Description of the Related Art
The development of microelectronic technologies has been accompanied by an increasingly systematic integration of complex electrical functions, hitherto located outside the package of the integrated circuit. Among these functions, mention may be made of microelectromechanical systems (MEMS) and passive components known to those skilled in the art as above-IC components produced above the passivation layer covering the integrated circuit.
The production of these MEMS systems or passive components requires strict compatibility, especially thermal compatibility, of their steps with those of the production of the lower interconnect levels, and a protective layer before the circuit is packaged.
At the present time, the incorporation of high-performance passive components and microelectromechanical systems is divided into two steps, namely the incorporation of the component on the one hand and the assembly with a protective cover on the other.
The production of the component takes place directly on the chip where the digital and analogue circuits are integrated, above an insulating passivation layer.
The protective cover is produced by means of an additional layer placed above the component, this additional layer having to allow it to be mechanically isolated from the external world without thereby degrading performance or preventing its movement, especially in the case of microelectromechanical systems. In addition, strict compatibility between the “chip/component/protective cover” stack and the standard packaging processes proves to be necessary, in particular in the case of electrical connection of the chip to the package. At the present time, processes are known which ensure one or other of these functions.
By way of indication, mention may be made of the process known to those skilled in the art by the name “flip-chip”. This process involves contacts which ensure the mechanical integrity of the stack and the electrical connection between the chip and the lower face of the cover. More specifically, a wafer, aligned with respect to the passivation layer on which the component has been produced, is bonded by partial fusion at a moderate temperature with the aid of solder bumps which then serve as support. This flip-chip procedure damages neither the interconnects nor the component to be covered. However, the discrete nature of the solder bumps does not protect the side walls of the component, for example a microswitch.
According to a second approach, again after having produced the component on the passivation layer covering the integrated circuit, the component is covered with a wafer in which a cavity intended to receive the component has been made. This wafer is fixed to the passivation layer of the integrated circuit with the aid of a polymer material which acts as adhesive. Mechanical isolation is complete. On the other hand, the two wafers remain electrically isolated and only localized etching of the cover above the contact pads will allow contact with the lower circuit by means of additional steps during packaging.
Thus, in the prior art, no method allows both the component to be protected and the electrical contacting, indispensable for packaging, to be guaranteed.
Added to this limitation are further drawbacks which are associated with the contemplated approach and which complicate the integration.
This is because the component is produced above the electronic chip. To avoid any damage to the lower interconnect levels, this production must not involve temperatures above 450° C. However, this constraint in particular prevents the use of specific materials, such as certain dielectrics having a very high permittivity.
Moreover, the processes of the prior art finally end up with a stack substantially greater than 500 microns in height, which no longer allows the standard packaging procedures to be applied. It is then necessary to thin the cover, but its handling then becomes a tricky operation because of its mechanical fragility.
Moreover, once the wafers have been assembled, it becomes difficult to perform further technological operations because of the non-uniformity of the thickness of the adhesive polymer and of the solder bumps which mean that the upper surface has a poor flatness.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.